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PRELIMINARY DATA SHEET
128MB Registered DDR SDRAM DIMM
EBD12RB8ALFA (16M words x 72 bits, 1 Bank)
Description
The EBD12RB8ALFA is a 16M x 72 x 1 bank Double Data Rate (DDR) SDRAM Module, mounted 9 pieces of 128M bits DDR SDRAM (EDD1208ALTA) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). Read and write operations are performed at the cross points of the CLK and the /CLK. This high-speed data transfer is realized by the 2bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 184-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
* 184-pin socket type dual in line memory module (DIMM) Outline: 133.35mm (Length) x 43.18mm (Height) x 4.00mm (Thickness) Lead pitch: 1.27mm * 2.5V power supply (VDD/VDDQ) * SSTL-2 interface for all inputs and outputs * Clock frequency: 133MHz/100MHz (max.) * Data inputs and outputs are synchronized with DQS * 4 banks can operate simultaneously and independently (Component) * Burst read/write operation * Programmable burst length: 2, 4, 8 Burst read stop capability * Programmable burst sequence Sequential Interleave * Start addressing capability Even and Odd * Programmable /CAS latency (CL): 2, 2.5 * 8192 refresh cycles: 15.6s (4096/64ms) * 2 variations of refresh Auto refresh Self refresh
Document No. E0212E10 (Ver. 1.0) Date Published August 2001 Printed in Japan URL: http://www.elpida.com
C
Elpida Memory, Inc. 2001
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
EBD12RB8ALFA
Ordering Information
Part number EBD12RB8ALFA-7A EBD12RB8ALFA-75 EBD12RB8ALFA-1A Clock frequency MHz (max.) 133 133 100 /CAS latency 2.0 2.5 2.0 Package Contact pad Mounted devices EDD1208ALTA
184-pin dual lead Gold out socket type
Pin Configurations
Front side 1 pin 52 pin 53 pin 92 pin
93 pin Back side
144 pin 145 pin 184 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Pin name VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ NC NC VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7
Pin No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Pin name DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS NC
Pin No. 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121
Pin name VSS DQ4 DQ5 VDDQ DM0/DQS9 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1/DQS10 VDD DQ14 DQ15 NC VDDQ NC DQ20 NC VSS DQ21 A11 DM2/DQS11 VDD DQ22
Pin No. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167
Pin name VSS DM8/DQS17 A10 CB6 VDDQ CB7 VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS DQ44 /RAS DQ45 VDDQ /CS0 NC DM5/DQS14 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC
Preliminary Data Sheet E0212E10 (Ver. 1.0)
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EBD12RB8ALFA
Pin No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Pin name VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Pin name NC VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin No. 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Pin name A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DM3/DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CLK0 /CLK0 Pin No. 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Pin name VDD DM6/DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
Preliminary Data Sheet E0212E10 (Ver. 1.0)
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EBD12RB8ALFA
Pin Description
Pin name A0 to A11 BA0, BA1 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0 CKE0 CLK0 /CLK0 DQS0 to DQS8 DM0 to DM8/DQS9 to DQS17 SCL SDA SA0 to SA2 VDD VDDQ VDDSPD VREF VSS VDDID /RESET NC Function Address input Row address Column address A0 to A11 A0 to A9, A11
Bank select address Data input/output Check bit (Data input/output) Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input and output data strobe Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for DQ circuit Power for serial EEPROM Input reference voltage Ground VDD indentication flag Reset pin (forces register inputs low) No connection
Preliminary Data Sheet E0212E10 (Ver. 1.0)
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EBD12RB8ALFA
Serial PD Matrix
Byte No. 0 1 2 3 4 5 6 7 8 9 Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM banks Module data width Module data width continuation Bit7 Bit6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 Bit5 Bit4 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 Bit3 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit2 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 1 0 0 Bit1 Bit0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 Hex value 80H 08H 07H 0CH 0AH 01H 48H 00H 04H 75H 75H A0H 75H 75H 80H 02H 80H 08H 08H 01H 0EH 04H 0CH 01H 02H 26H 00H 75H A0H A0H 75H 75H 80H 00H Comments 128 bytes 256 bytes DDR SDRAM 12 10 1 72 bits 0 SSTL 2 7.5ns 7.5ns 10ns 0.75ns 0.75ns 0.8ns ECC Norm x8 x8 1 CLK 2, 4, 8 4 2, 2.5 0 1 Reg+PLLdifclk VDD 0.2V 7.5ns 10ns 10ns 0.75ns 0.75ns 0.8ns
Voltage interface level of this assembly 0 DDR SDRAM cycle time, CL = 2.5 (-7A) (-75) (-1A) 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1
10
SDRAM access from clock (tAC) (-7A) (-75) (-1A)
11 12 13 14 15 16 17 18 19 20 21 22 23
DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency SDRAM module attributes SDRAM Device Attributes: General Minimum clock cycle time at CL = 2 (-7A) (-75) (-1A)
24
Maximum data access time (tAC) from clock at CL = 2 0 (-7A) (-75) (-1A) 0 1 0
25 to 26
Preliminary Data Sheet E0212E10 (Ver. 1.0)
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EBD12RB8ALFA
Byte No. 27 Function described Minimum row precharge time (tRP) (-7A) (-75) (-1A) 28 Bit7 Bit6 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 Bit5 Bit4 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 1 1 1 0 Bit3 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 Bit2 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 Bit1 Bit0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Hex value 50H 50H 50H 3CH 3CH 3CH 50H 50H 50H 2DH 2DH 32H 20H 90H 90H B0H 90H 90H B0H 50H 50H 60H 50H 50H 60H 00H 00H 89H B4H 5AH FEH 00H Elpida Memory Comments 20ns 20ns 20ns 15ns 15ns 15ns 20ns 20ns 20ns 45ns 45ns 50ns 128Mbytes 0.9ns 0.9ns 1.1ns 0.9ns 0.9ns 1.1ns 0.5ns 0.5ns 0.6ns 0.5ns 0.5ns 0.6ns
Minimum row active to row active delay (tRRD) 0 (-7A) (-75) (-1A) 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
29
Minimum /RAS to /CAS delay (tRCD) (-7A) (-75) (-1A)
30
Minimum active to precharge time (tRAS) (-7A) (-75) (-1A)
31 32
Module bank density Address and command setup time before clock (tIS) (-7A) (-75) (-1A)
33
Address and command hold time after clock (tIH) (-7A) (-75) (-1A)
34
Data input setup time before clock (tDS) 0 (-7A) (-75) (-1A) 0 0 0 0 0 0 0 1 1 0 1 0
35
Data input hold time after clock (tDH) (-7A) (-75) (-1A)
36 to 61 62 63
Superset information SPD Revision Checksum for bytes 0 to 62 (-7A) (-75) (-1A)
64 65 to 71 72 73 to 90 91 to 92 93 to 94 95 to 98
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Manufacturer's Part number Revision code Manufacturing date Assembly serial number
Preliminary Data Sheet E0212E10 (Ver. 1.0)
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EBD12RB8ALFA
Byte No. 99 to 127 Function described Manufacture specific data Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Block Diagram
/RCS0 DQS0 DM0/DQS9 DQS4 DM4/DQS13
DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
DQS1 DM1/DQS10
DQ 0 DM /CS DQS DQ 1 D0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39
DQS5 DM5/DQS14
DQ 0 DM /CS DQS DQ 1 D4 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15
DQS2 DM2/DQS11
DQ 0 DM /CS DQS DQ 1 D1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47
DQS6 DM6/DQS15
DQ 0 DM /CS DQS DQ 1 D5 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23
DQS3 DM3/DQS12
DQ 0 DM /CS DQS DQ 1 D2 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55
DQS7 DM7/DQS16
DQ 0 DM /CS DQS DQ 1 D6 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31
DQS8 DM8/DQS17
DQ 0 DM /CS DQS DQ 1 D3 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
DQ 0 DM /CS DQS DQ 1 D7 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
SERIAL PD
CB 0 CB 1 CB 2 CB 3 CB 4 CB 5 CB 6 CB 7
DQ 0 DM /CS DQS DQ 1 D8 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
SCL A0 A1 A2
SDA
SA0 SA1 SA2
/CS0 BA0, BA1 A0 to A11 /RAS /CAS CKE0 /WE PCK /PCK Register
/RCS0 RBA0, RBA1 RA0 to RA11 /RRAS /RCAS RCKE0 /RWE /RESET
/CS0 : D0 to D8 BA0, BA1 : D0 to D8 A0 to A11 : D0 to D8 /RAS : D0 to D8 /CAS : D0 to D8 CKE : D0 to D8 /WE : D0 to D8
VDDQ VDD VREF VSS VDDID
D0 to D8 D0 to D8 D0 to D8 D0 to D8
CLK0, /CLK0
PLL
*
Note :
Wire per Clock loading table/Wiring diaglams.
Remarks : 1. The value of all resistors of DQs, DQSs, DM/DQSs is 22 . : 2. D0 to D8: EDD1208ALTA (4M words 8 bits 4 banks)
Preliminary Data Sheet E0212E10 (Ver. 1.0)
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EBD12RB8ALFA
Differential Clock Net Wiring (CLK0, /CLK0)
0ns (nominal) SDRAM stack 120
PLL OUT1
CLK0
120 IN
SDRAM stack 240 Register1
/CLK0
120 C
OUT'N'
(Typically two registers per DIMM)
Feedback
240
Register2
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl be set to 0 ns (nominal). 2. Input, output and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. 4. Termination resistors for feedback path clocks are located after the pins of the PLL.
Preliminary Data Sheet E0212E10 (Ver. 1.0)
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EBD12RB8ALFA
Pin Functions (1)
CLK, /CLK (input pin): The CLK and the /CLK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CLK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CLK and the /CLK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CLK and the /CLK. /CS (input pin): When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins): These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A11 (input pins): Row address (AX0 to AX11) is determined by the A0 to the A11 level at the cross point of the CLK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11) is loaded via the A0 to the A9, the A11 at the cross point of the CLK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled. BA0, BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected. CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. The CKE level must be kept for 1 CLK cycle (= LCKEPW) at least, that is, if CKE changes at the cross point of the CLK rising edge and the VREF level with proper setup time tIS, at the next CLK rising edge CKE level must be kept with proper hold time tIH.
Pin Functions (2)
DQ, CB (input and output pins): Data are input to and output from these pins. DQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input). VDD and VDDQ (power supply pins): 2.5V is applied. (VDD is for the internal circuit and VDDQ is for the output buffer.) VDDSPD (power supply pin): 2.5V is applied (For serial EEPROM). VSS (power supply pin): Ground is connected. /RESET (input pin): LVCMOS reset input. When /RESET is low, all registers are reset and all outputs are low.
Detailed Operation Part, AC Characteristics and Timing Waveforms
Refer to the EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Series datasheet (E0136E). DM pins of component device fixed to VSS level on the module board. DIMM /CAS latency = Device CL + 1 for registered type.
Preliminary Data Sheet E0212E10 (Ver. 1.0)
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EBD12RB8ALFA
Electrical Specifications
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VDD, VDDQ IO PD TA Tstg Value -0.5 to +3.6 -0.5 to +3.6 50 21 0 to +70 -55 to +125 Unit V V mA W C C Note 1 1
Notes: 1. Respect to VSS. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = 0 to +55C)
Parameter Supply voltage Symbol VDD, VDDQ VSS Input reference voltage Termination voltage DC Input high voltage DC Input low voltage DC Input signal voltage DC differential input voltage VREF VTT VIH VIL VIN (dc) min. 2.3 0 0.49 x VDDQ VREF - 0.04 VREF + 0.18 -0.3 -0.3 Typ 2.5 0 -- VREF -- -- -- -- max. 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.18 VDDQ + 0.3 VDDQ + 0.6 Unit V V V V V V V V 1 1 1, 3 1, 4 5 6 Notes 1, 2
VSWING (dc) 0.36
Notes: 1. 2. 3. 4. 5. 6.
All parameters are referred to VSS, when measured. VDDQ must be lower than or equal to VDD. VIH is allowed to exceed VDD up to 4.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to -1.0V for the period shorter than or equal to 5ns. VIN (dc) specifies the allowable dc execution of each differential input. VSWING (dc) specifies the input differential voltage required for switching.
Preliminary Data Sheet E0212E10 (Ver. 1.0)
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EBD12RB8ALFA
DC Characteristics (TA = 0 to 55C, VDD, VDDQ = 2.5V 0.2V, VSS = 0V)
Parameter Operating current (ACTV-PRE) Symbol ICC0 Grade -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A max. TBD Unit mA Test condition CKE VIH, tRC = tRC (min.) CKE VIH, BL = 2, CL = 3.5, tRC = tRC (min.) CKE VIL Notes 1, 2, 5
Operating current (ACTV-READICC1 PRE) Idle power down standby current ICC2P
TBD
mA
1, 2, 5
TBD
mA
4
Idle standby current Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current
ICC2N
TBD
mA
CKE VIH, /CS VIH
4
ICC3P
TBD
mA
CKE VIL CKE VIH, /CS VIH tRAS = tRAS (max.) CKE VIH, BL = 2, CL = 3.5 CKE VIH, BL = 2, CL = 3.5 tRFC = tRFC (min.) Input VIL or VIH Input VDD - 0.2V Input 0.2V.
3
ICC3N
TBD
mA
3
ICC4R
TBD
mA
1, 2, 5, 6
ICC4W
TBD
mA
1, 2, 5, 6
ICC5
TBD
mA
Self refresh current
ICC6
TBD
mA
Notes. 1. 2. 3. 4. 5. 6. 7.
These ICC data are measured under condition that DQ pins are not connected. One bank operation. One bank active. All banks idle. Command/Address transition once per one cycle. Data/Data mask transition twice per one cycle. The ICC data on this table are measured with regard to tCK = tCK (min.) in general.
DC Characteristics2 (TA = 0 to 70C, VDD, VDDQ = 2.5V 0.2V, VSS = 0V)
Parameter Input leakage current Output leakage current Output high current Output low current Symbol ILI ILO IOH IOL min. -10 -5 -15.2 15.2 max. 10 5 -- -- Unit A A mA mA Test condition VDD VIN VSS VDD VOUT VSS VOUT = 1.95V VOUT = 0.35V Notes
Preliminary Data Sheet E0212E10 (Ver. 1.0)
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EBD12RB8ALFA
Pin Capacitance (TA = 25C, VDD, VDDQ = 2.5V 0.2V)
Parameter Input capacitance Input capacitance Data and DQS input/output capacitance Symbol CI1 CI2 CO Pins max. Unit pF pF pF Notes 1, 3 1, 3 1, 2, 3
Address, /RAS, /CAS, /WE, TBD /CS, CKE CLK, /CLK DQ, DQS, CB TBD TBD
AC Characteristics Synchronous Characteristics
-7A Parameter Clock cycle time CL = 2.5 CL = 2 CLK high-level width CLK low-level width DQ output access time from CLK, /CLK DQS output access time from CLK, /CLK tCH tCL tAC Symbol tCK min. 7.5 7.5 0.45 0.45 -0.75 max. 12 12 0.55 0.55 0.75 0.75 0.5 0.5 0.75 0.75 -- 1.1 0.6 -75 min. 7.5 10 0.45 0.45 -0.75 -0.75 -- -- -0.75 -0.75 tCH, tCL 0.9 0.4 max. 12 12 0.55 0.55 0.75 0.75 0.5 0.5 0.75 0.75 -- 1.1 0.6 -1A min. 10 10 0.45 0.45 -0.8 -0.8 -- -- -0.8 -0.8 max. 12 12 0.55 0.55 0.8 0.8 0.6 0.6 0.8 0.8 Unit ns ns tCK tCK ns ns ns ns ns ns ns tCK tCK ns ns ns ns ns tCK tCK tCK tCK tCK tCK tCK ns ns ns tCK Note
tDQSCK -0.75 --
DQS-DQ skew (for DQS and associated DQ tDQSQ signals)
DQS-DQ skew (for DQS and all DQ signals) tDQSQA -- Data out low-impedance time from CLK, /CLKtLZ Data out high-impedance time from CLK, /CLK Half clock period Read preamble Read postamble DQ/DQS output hold time from DQS DQ and DM input setup time DQ and DM input hold time tHZ tHP tRPRE tRPST tQH tDS tDH -0.75 -0.75 tCH, tCL 0.9 0.4
tCH, tCL -- 0.9 0.4 1.1 0.6
tHP - 0.75 -- 0.5 0.5 1.75 -- -- -- -- -- 0.6 1.25 -- -- -- -- -- -- -- --
tHP - 0.75 -- 0.5 0.5 1.75 0 0.25 0.4 0.75 0.35 0.35 0.2 0.2 0.9 0.9 2.2 1 -- -- -- -- -- 0.6 1.25 -- -- -- -- -- -- -- --
tHP - 1 -- 0.6 0.6 2 0 0.25 0.4 0.75 0.35 0.35 0.2 0.2 1.1 1.1 2.5 1 -- -- -- -- -- 0.6 1.25 -- -- -- -- -- -- -- --
DQ and DM input pulse width (for each input) tDIPW Write preamble setup time Write preamble Write postamble Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CLK setup time DQS falling edge hold time from CLK Address and control input setup time Address and control input hold time Address and control input pulse width Internal write to read command delay
tWPRES 0 tWPRE tWPST tDQSS tDQSH tDQSL tDSS tDSH tIS tIH tIPW tWTR 0.25 0.4 0.75 0.35 0.35 0.2 0.2 0.9 0.9 2.2 1
Preliminary Data Sheet E0212E10 (Ver. 1.0)
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EBD12RB8ALFA
Synchronous Characteristics Example
tCK Symbol tCH tCL tRPRE tRPST tWPRE tWPST tDQSS tDQSH tDQSL tDSS tDSH tWTR 7.5 ns min. 3.4 3.4 6.75 3 0.25 3 5.6 2.63 2.63 1.5 1.5 7.5 max. 4.1 4.1 8.25 4.5 -- 4.5 9.4 -- -- -- -- -- 10 ns min. 4.5 4.5 9 4 2.5 4 7.5 3.5 3.5 2 2 10 max. 5.5 5.5 11 6 -- 6 12.5 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
Asynchronous Characteristics
-7A Parameter ACT to REF/ACT command period (operation) REF to REF/ACT command period (refresh) ACT to PRE command period PRE to ACT command period ACT to READ/WRITE delay ACT(one) to ACT(another) command period Write recovery time Auto precharge write recovery time + precharge time Mode register set command cycle time Exit self refresh to command Average periodic Refresh interval Symbol tRC tRFC tRAS tRP tRCD tRRD tWR tDAL tMRD tXSNR tREF1 min. 65 75 45 20 20 15 2 TBD 15 75 -- max. -- -- 120,000 -- -- -- -- -- -- -- 15.6 -75 min. 65 75 45 20 20 15 2 TBD 15 75 -- max. -- -- 120,000 -- -- -- -- -- -- -- 15.6 -1A min. 70 80 50 20 20 15 2 TBD 15 80 -- max. -- -- 120,000 -- -- -- -- -- -- -- 15.6 Unit ns ns ns ns ns ns CLK ns ns ns s
Preliminary Data Sheet E0212E10 (Ver. 1.0)
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Physical Outline
Unit: mm 133.35 0.15 128.95 4.00 max (64.48) (DATUM -A-)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Front) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 1 92
B 64.77 49.53 A
; ; ; ; ; ; ;
2.30
1.27 0.10
2 - 2.50 0.10
4.00 0.10
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Back) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 3.00 min
93 184 R 2.00
10.00
4.00 min 43.18 0.15 17.80
Detail A
2.50 0.20
Detail B 1.27 typ 6.62
0.20 0.15
(DATUM -A-) 2.175 R 0.90
6.35
3.80
1.00 0.05
1.80 0.10
Note: Tolerance on all dimensions 0.13 unless otherwise specified.
Preliminary Data Sheet E0212E10 (Ver. 1.0)
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EBD12RB8ALFA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0107
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E0212E10 (Ver. 1.0)
15
EBD12RB8ALFA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
Preliminary Data Sheet E0212E10 (Ver. 1.0)
16

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